Hardware Simulation, Chisel, FIRRTL, Agile Hardware Development, Code Generation, Verification.
– For high-performance simulation (e.g., running firmware on a CPU design), Chisel can generate Verilog, which is then fed into Verilator. Verilator compiles it into C++ models, achieving speeds 10–100× faster than Treadle. Chisel’s test harness can then drive this compiled model via a JNI (Java Native Interface) bridge. chiselsim